The present invention relates to a semiconductor integrated circuit device and a technique for fabricating the device and, more particularly, to a technique which is effective when applied to a semiconductor integrated circuit device having a DRAM (i.e., Dynamic Random Access Memory) equipped with an information storing capacity element (or capacitor) having the multi-layered fin structure.
A large-capacity DRAM of recent years has adopted the stack structure, in which the information storing capacity element is arranged over the memory cell selecting MISFET, so as to compensate such a reduction of the quantity (Cs) of stored electric charge of the information storing capacity element as occurs according to the fine structure of the memory cells. Above all, the DRAM having the multi-layered fin structure in the storage electrode of the information storing capacity element has its application promoted to a larger capacity on and after 16 Mbits, because its surface area can be remarkably enlarged.
The DRAM having the information storing capacity element of the aforementioned multi-layered fin structure is exemplified in the prior art by Japanese Patent Laid-Open No. 53262/1992. The DRAM, as disclosed in this Laid-Open, is formed with three-layered fins in the storage electrode of the information storing capacity element. In this DRAM, moreover, the clearance between the storage electrode and the storage electrode of an adjoining memory cell is made narrower in the lower-layer fin and wider in the upper-layer fin so that the inter-layer insulating film to be deposited in that clearance may be cleared of any "void" to improve the reliability of the DRAM.
In order to form the aforementioned three-layered fins, a photoresist is formed over three-layered polycrystalline silicon films deposited across the inter-layer insulating film and is formed in its portion with a hole, and the uppermost polycrystalline silicon film exposed to the bottom of that hole is isotropically etched with an etching liquid to form the uppermost-layer fin.
Next, the inter-layer insulating film between the uppermost-layer fin and the second-layered polycrystalline silicon film is formed with a hole, and the second-layered polycrystalline silicon film exposed to the bottom of that hole is isotropically etched with an etching liquid to form a second-layer fin.
Subsequently, the inter-layer insulating film between the second-layer fin and the uppermost polycrystalline silicon film is formed with a hole by a method similar to the aforementioned one, and the lowermost polycrystalline silicon film exposed to the bottom of that hole is isotropically etched with an etching liquid to form a lowermost-layer fin. After this, the inter-layer insulating films left between the individual fins are etched off to form the storage electrode having the three-layered fins.
According to the process described above, the uppermost polycrystalline silicon film (or fin) is exposed to the etching liquid for a longer time period than the lower polycrystalline silicon films (or fins) so that its sides are more etched. As a result, there is attained the storage electrode in which the clearance between the fins of the adjoining memory cells is the wider for the upper fins.